A semiconductor memory cell typically includes a storage device for storing data and an access device for accessing the data stored in the storage device.
In DRAM memory cells, data is stored by charging or discharging a storage capacitor. In stacked capacitor type memory cells, the capacitors are placed above the access devices. In trench capacitor type memory cells, the storage devices are buried in the substrate in which the access transistors are formed.
Typically the access devices are field-effect transistors (FETs). Active areas of the access transistors are formed in a single crystalline semiconductor substrate such as a silicon wafer. The active areas comprise a first doped region defining a first source/drain region, a second doped region defining a second source/drain region and a channel region between the first and the second source/drain-region. The first and the second doped region are of a first conductivity type. The channel region is not doped or is of a second conductivity type that is the opposite of the first conductivity type.
The first doped region forms a bit line contact section and is coupled to a bit line. The bit line transmits data to and from the memory cell. The second doped region forms a storage node contact section and is connected to a storage node electrode of the capacitor.
The access transistor is controlled by a voltage applied to a gate electrode, which for planar transistor devices is arranged above a pattern surface of the substrate and which is adjacent to the respective channel section. A gate dielectric insulates the gate electrode from the channel region. The electric potential of the gate electrode controls the charge carrier distribution by capacitive coupling in the adjoining channel section. The gate electrodes of the access transistors of a plurality of memory cells are connected and form a connectivity line (word line) for addressing a group of memory cells within a memory cell array.
When a voltage higher than a threshold voltage is applied to the gate electrode, an enhancement zone of mobile charge carriers is induced in the channel section, wherein the charge carriers form a conductive channel in the channel section between the storage node contact section and the bit line contact section. The conductive channel connects the storage node electrode of the capacitor to the bit line. When a voltage lower than the threshold voltage is applied to the gate electrode, the storage node electrode of the capacitor remains insulated from the bit line.
Planar field effect transistors do not scale down well to sub 100 nanometer technologies, which use a feature size of photolithographic patterns of less than 100 nanometers. A maximum packaging density requires a maximum channel length, which corresponds to the minimum feature size. At channel lengths below 100 nanometers, short channel effects occur, for example sub-threshold leakage current.
In U.S. Pat. No. 5,945,707, the disclosure of which is incorporated herein by reference, a recessed channel array transistor (RCAT) with enhanced effective channel length is described. The first and second source/drain regions are arranged in a horizontal plane parallel to the pattern surface of the semiconductor substrate. Between the first and the second source/drain region a gate groove is etched into the semiconductor substrate. A gate electrode is disposed within the groove. A gate dielectric extends along the semiconductor sidewalls of the gate groove and separates the gate electrode from the channel region. In a conducting state of the RCAT, the channel extends in a first vertical section from the first doped region downwards along the first sidewall of the gate groove, crosses beneath the gate groove in horizontal direction and extends then in a second vertical section along a second sidewall of the gate groove upwards to the second doped region. The effective channel length of a RCAT is a function of the depth of the gate groove and the planar distance between both source/drain regions.
A sphere-shaped RCAT (S-RCAT) with enhanced effective channel length is described in “High-Density Low-Power-Operating DRAM Device Adopting 6F2 Cell Scheme with Novel S-RCAT Structure on 80 nm Feature Size and Beyond”; by H. J. Oh et al.; IEEE Proceedings of ESSDERC; Grenoble, France; 2005. The gate groove is expanded in the bottom section. The effective channel length of the S-RCAT is enhanced, whereas the planar dimensions remain unmodified, such that the S-RCAT enables further enhanced packaging densities.
At maximum packaging density, the effective channel width of a RCAT is equal to the minimum lithographic feature size. The effective channel width corresponds to the resistance of the transistors in the conducting state (Ron) and affects the switching characteristics of the memory cell.
A RCAT with corner gate device is therefore proposed in German Patent No. DE 103 61 695 B3, the disclosure of which is incorporated herein by reference. Corner sections of a gate electrode partly wrap around a semiconductor fin, which comprises the active area. The corner sections of the gate electrode extend along sections of vertical sidewalls of the semiconductor fin. In the conducting state of the RCAT, the channel is formed both along the sidewalls of the gate groove and along the sidewalls on the long sides of the semiconductor fin. The channel width is increased by the portion of the channel that extends along the sidewalls of the semiconductor fin. Due to the increased channel width, RCATs with FinFET-like corner gate devices, also known as extended U-groove transistors (EUT), show a lower On-Resistance Ron and faster switching properties.
A method of manufacturing a RCAT with corner gate device is described in German Patent No. DE 103 61 695 B3. According to that method, a stripe-shaped semiconductor fin with a first and a second vertical sidewall on the long sides of the fin is formed in a single crystalline silicon substrate. Shallow trench isolations made of silicon oxide are formed on both long sides of the fin. The short sides of the fin define a first and a second end of the fin. Between the first and the second end of the fin, a gate groove is etched into the semiconductor fin, which extends from one long side of the fin to the other. An isotropic oxide etch process is performed. The etching pulls back the shallow trench isolations from the long sides of the semiconductor fin, wherein the pullback starts from the intersecting plane between the gate groove and the shallow trench isolations. The recess leaves pockets in the shallow trench isolation, which are adjacent to the gate groove. A gate oxide is grown on the semiconductor fin. The gate groove and the pockets are filled with a gate conductor material. In the upper section of the fin, the first source/drain region is formed at the first end of the fin, and the second source/drain region is formed at the second end of the fin by implanting ions.
Capacitive coupling between the gate electrode and the source/drain regions deteriorates the switching characteristics of the transistor.
A method for fabricating an insulator collar between the source/drain regions and the gate electrode of a RCAT with corner gate device is described in U.S. patent application Ser. No. 11/222,613, the disclosure of which is incorporated herein by reference.
A first gate conductor material is recessed after deposition such that the first gate conductor material fills only a bottom portion of the gate groove and the pockets respectively. An insulator collar is provided on the exposed portions of the semiconductor fin above the recessed first gate conductor material. The thickness of the insulator collar is greater than the thickness of the gate oxide. Then, a second gate conductor material is deposited on top of the recessed first gate conductor material. When polycrystalline silicon (polysilicon) is used as the first and the second gate conductor material, a polysilicon-polysilicon interface within the gate groove results from this method, wherein the polysilicon-polysilicon interface disadvantageously deteriorates the electrical resistance of the gate electrode structure.
Experimental results for RCATs fabricated according to the described method show inferior switching characteristics and a wider range for the switching characteristics among a plurality of devices that emerge from the same substrate than expected. Therefore a need exists for a method of fabricating a recessed channel array transistor with corner gate device which provides enhanced switching characteristics and which reduces a deviation of the switching characteristics among the members of a plurality of RCATs formed on the same substrate.